1. Field of the Invention
An object of the present invention is a method to program the memory cells of a memory as well as a circuit to implement this method. It particularly concerns memories for which the memory cells comprise floating-gate transistors and for which the programming is got by an electrical field effect. More particularly, these memories are EEPROM memories, as distinct from EPROM memories for which the programming of the memory cells requires a saturation of the conduction channel of the floating-gate transistor acting as the memorizing element of these memory cells. In a special application, the programming method is more particularly used in "page mode". In this type of mode, several memory cells, connected to one and the same word line of the memory plane, are programmed at the same time. Furthermore, the invention is more particularly designed for programming operations in which high voltages are brought into play.
2. Description of the Prior Art
In the prior art, the programming of the floating-gate transistor of an EEPROM type memory cell is got by subjecting the drain and source regions of this transistor to a high potential as compared with a potential to which is subjected the control gate of this transistor, superimposed on the floating gate. For this programming purpose, the floating gate has a starting up boss used locally, at the boss itself, to increase the value of the electrical field induced by this difference in potential. Under the effect of this progamming electrical field, particles, namely electrons, leave the floating gate. Subsequently, when the transistor of this memory cell is subjected to normal action, in being powered or controlled, it stays on or goes off depending on whether or not it has been programmed by the migrations of electrons. Hence, for a transistor to be programmed, one of its regions (and necessarily the region close to the starting up boss) must be subjected to a high voltage VPP. This programming is erased by applying the high voltage VPP to the control gate and the low voltage to one of the regions (on the drain).
In practice, if the supply voltage of an integrated circuit of the EEPROM type is about 5 volts, VPP is about 20 volts. These EEPROM type circuits, especially in applications with memory cards using integrated circuits, are generally provided with internal generators for setting up the potential VPP. These generators, may, for example, comprise generators of the SHENKEL type. At high voltages, generators of this type cannot withstand a static consumption level exceeding a few microamperes. To enable the programming operation, it is customary to assist these generators, at every point where they distribute their high potential, by means of charge pumps. As seen in FIG. 1, a charge pump essentially comprises a transistor T1 connected, firstly, to the potential VPP generator and, secondly, at the point A, to a capacitor C. A native transistor T2 (with a threshold voltage VT=0) is connected, firstly, to the terminal A and, secondly, by the terminal B to the control gate of the transistor T1. At the other terminal of the capacitor C, a pulse signal is introduced, varying at a high rate between VCC and 0. This signal is, for example, a 5 MHz clock signal. The control gate of the transistor T2 is connected to the point A. A third transistor T3, the control gate of which is connected to the potential VCC, receives, firstly, a signal SBL which, depending on its state, marks the intention to program a memory cell. Secondly, the transistor T3 is connected to the point B. The point B is further connected to a bit line LB which ends in the source regions of the floating-gate transistors of the memory cells to be programmed.
If a bit line is not to be selected, for example because none of the memory cells connected to it is to be programmed, the signal SBL is equal to zero. If the signal SBL equals zero, the transistor T3 is in short circuit, and the point B and the bit line are at null potential, while the charge pump formed by the capacitor C and the transistor T2 delivers unnecessarily. However, the transistor T1 is off. If, on the contrary, the bit line is selected, if SBL equals VCC, it will be shown that the potential available at the bit line rises to VPP. More precisely, it rises to VPP+VT, VT being the threshold voltage of the transistor T1. Let it be assumed, for example, that when the pulse signal PHI is at zero, A is substantially equal to VCC. Under these conditions, since the transistor T2 is a native transistor, B is also substantially equal to VCC. Consequently, the transistor T3 is off. When the signal PHI rises to VCC, the capacitor CC transmits a voltage step and the potential of A rises, for example, by two volts. Under these conditions, the transistor T2 comes on and the potential at B follows the potential at A. When the signal PHI returns to zero, A undergoes a voltage drop which turns the transistor T2 off but turns the transistor T1 on. While the potential of B remains at the value which it has just reached and while the potential of A has decreased, the coming on of the transistor T1 forces the potential of A to rise. The potential of A increases substantially upto the value of the potential of B minus the drop in gate-source voltage in the transistor T1. For example, it can be assumed that A has thus gained one volt and has gone to 6 volts with respect to its previous situation. Continuing thus, at the rate of the pulses PHI, the potential of A and the potential of B rise to VPP (+VT). For, when the potential at B reaches VPP+VT, the node A, charged at each rising pulse of PHI, is discharged in the supply VPP by the transistor T1. When the potential of B has reached a sufficient level, the floating-gate transistor of the memory cell is programmed.
The drawback entailed by the existence of charge pumps is particularly felt when the memory is programmed in page mode, namely when it is sought to program all the bits belonging to one and the same word, i.e. all the bits belonging to different bit lines. The programming in page mode is valuable in itself because it enables access to several memory cells of the memory plane at the same time. For, in order to reduce the programming time related to one bit and inasmuch as the memory cells are distributed at the intersections of the bit lines and the word lines, it is preferable, rather than programming memory cells one after another, firstly, to select a set of bit lines and, secondly, to select a word line to program, at the same time, all the memory cells belonging to these bit lines and to this word line. It is then enough to change the word line to gain access to a new set of memory cells belonging to these bit lines and to this new word line.
In its principle, page mode programming makes it necessary for charge pumps to be assigned to each bit line of the memory plane. For, when the memory cells in a bit line have to be programmed, the concerned bit line is selected and its transistor T3 is off. By contrast, the memory cells which should not be programmed are placed on bit lines which, in correspondence, should not be selected: their transistor T3 should be on. If all the bit lines were to be connected to one and the same charge pump, it would delive to the non-selected bit lines transistors which are on, and none of the bit lines would have its potential rise to VPP. The complicated nature of the charge pumps and above all their bulk, namely the space that they occupy in a memory, are negative factors for the integration capacity of EEPROM type circuits.
An object of the invention is to overcome these drawbacks by eliminating the existence, at least to a great extent, of the charge pumps while, at the same time, enabling page mode programming operation in a preferred embodiment. In the invention, advantage is taken of the fact that the cells of an EEPROM type memory can be programmed without any consumption of current on the potential VPP because this programming is caused by an electrical field effect. In the method of the invention, before the programming, the selection of the bit lines is neutralized and, during this neutralizing process, all the bit lines are pre-charged at a high potential. Then the bit lines are selected by eliminating the neutralization. The potential of the non-selected bit lines naturally breaks down through their transistor T3 which is on. The potential of the selected bit lines does not break down because, with the pre-charging over, all the lines are then uncoupled from their VPP supply which may then break down. Finally, for the programming, a null potential is imposed on the control gates of the floating-gate transistors of the memory cells to be programmed. Under these conditions, only these transistors get programmed. It must be noted that these transistors were not programmed during the pre-charging process because, at that time, transistors providing access to the cells were off. They are turned off by a command applied to their control gate. In a preferred alternative, rather than selecting the control gates of the transistors of the memory cells to be programmed one after the other, a selection is made at the same time, and then a weak potential is imposed, at the same time, on all the control gates of the transistors connected to one and the same word line. Thus, the memory is programmed in page mode.